View FCD4B14_1401031.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features ? sensitive layer over a 0.8 m cmos array image zone: 0.4 x 14 mm = 0.02" x 0.55" image array: 8 x 280 = 2240 pixels pixel pitch: 50 m x 50 m = 500 dpi pixel clock: up to 2 mhz enabling up to 1780 frames per second die size: 1.7 x 17.3 mm operating voltage: 3v to 5.5v naturally protected against esd: > 16 kv air discharge power consumption: 20 mw at 3.3v, 1 mhz, 25c operating temperature range: 0c to +70c: c suffix resistant to abrasion: >1 million finger sweeps chip-on-board (cob) package or 20-lead ceramic dip available for development, with specific protective layer applications pda (access control, data protection) cellular phones, smartphone (access e-business) notebook, pc-add on (access control, e-business) pin code replacement automated teller machine, pos building access electronic keys (cars, home,...) portable fingerprint imaging for law enforcement tv access figure 1. fingerchip packages 20-pin, 0.3" dual-inline ceramic package (dip20) step for easy integration sensing area wire protection (not drawn) chip-on-board package (cob) thermal fingerprint sensor with 0.4 mm x 14 mm (0.02" x 0.55") sensing area and digital output (on-chip adc) FCD4B14 fingerchip ? rev. 1962c ? 01/02
2 FCD4B14 1962c ? 01/02 die attach is connected to pin 1 and 16, and must be grounded. fpl pin must be grounded. table 1. pin description for dip ceramic package pin number name type 1gndgnd 2 ave analog output 3tpppower 4vccpower 5 rst digital input 6 oe digital input 7 de0 digital output 8 de1 digital output 9 de2 digital output 10 de3 digital output 11 fpl gnd 12 do3 digital output 13 do2 digital output 14 do1 digital output 15 do0 digital output 16 gnd gnd 17 ackn digital output 18 pclk digital input 19 tpe digital input 20 avo analog output gnd 2 3 4 5 6 7 8 9 avo tpe pclk ackn do0 do1 do2 do3 fpl 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ave tpp vcc rst oe de0 de1 de2 de3 gnd
3 FCD4B14 1962c ? 01/02 die attach is connected to pin 1, 7 and 21, and must be grounded. fpl pin must be grounded. ta ble 2. pin description for chip-on-board package pin number name type 1gndgnd 2 ave analog output 3 avo analog output 4tpppower 5 tpe digital input 6 vcc power 7gndgnd 8 rst digital input 9 pclk digital input 10 oe digital input 11 ackn digital output 12 de0 digital output 13 do0 digital output 14 de1 digital output 15 do1 digital output 16 de2 digital output 17 do2 digital output 18 de3 digital output 19 do3 digital output 20 fpl gnd 21 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 gnd ave avo tpp tpe vcc gnd rst pclk oe ackn de0 do0 de1 do1 de2 do2 de3 do3 fpl gnd
4 FCD4B14 1962c ? 01/02 description FCD4B14 is part of the fingerchip atmel monolithic fingerprint sensor family for which no optics, no prism and no light source are required. FCD4B14 is a single chip, high performance, low cost sensor based on temperature physical effects for fingerprint sensing. FCD4B14 has a linear shape, allowing for the capture of a fingerprint image by sweep- ing the finger across the sensing area. after capturing several images, atmel proprietary software can reconstruct a full 8-bit fingerprint image, if needed. FCD4B14 has a small surface combined with cmos technology, and a chip-on-board or ceramic dual-in-line package assembly. these facts contribute to a low-cost device. FCD4B14 delivers a programmable number of images per second, while an integrated analog to digital converter delivers a digital signal adapted to interfaces such as an epp parallel port, usb microcontroller or directly to micro-processors. thus, no frame grabber or glue interface is necessary to send the frames. these facts make FCD4B14 an easy device to include in any system for identification or verification applications. note: 1. absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operat- ing conditions. long exposure to maximum ratings may affect device reliability. table 3 . absolute maximum ratings (1) parameter symbol comments value unit positive supply voltage v cc gnd to 6.5 v temperature stabilization power tpp gnd to 6.5 v front plane fpl gnd to v cc v digital input voltage rst pclk gnd to v cc v storage temperature t stg -50 to +85 c lead temperature (soldering, 10 seconds.) t leads do not solder dip: socket mandatory forbidden c table 4 . recommended conditions of use parameter symbol comments min typ max unit positive supply voltage v cc 3v 5v 5.5v v front plane fpl must be grounded gnd v digital input voltage cmos levels v digital output voltage cmos levels v digital load c l 50 pf analog load c a r a not connected pf k ? operating temperature range t amb civil: ? c ? grade 0 to +70 c maximum current on tpp itpp 0 100 ma
5 FCD4B14 1962c ? 01/02 table 5 . resistance parameter min value standard method esd on pins. hbm (human body model) cmos i/o 2 kv mil-std-883- method 3015.7 on die surface (zapgun) air discharge 16 kv nf en 6100-4-2 mechanical abrasion number of cycles without lubricant multiply by a factor of 20 for correlation with a real finger 200 000 mil e 12397b chemical resistance cleaning agent, acid, grease, alcohol, diluted acetone 4 hours internal method table 6 . specifications explanation of test levels i 100% production tested at +25 c ii 100% production tested at +25 c, and sample tested at specified temperatures (ac testing done on sample) iii sample tested only iv parameter is guaranteed by design and/or characterization testing v parameter is a typical value only vi 100% production tested at temperature extremes d 100% probe tested on wafer at t amb =+25 c parameter symbol test level min typ max unit resolution iv 50 micron size iv 8x280 pixel yield: number of bad pixels i 15 bad pixels equivalent resistance on tpp pin i 23 30 47 ?
6 FCD4B14 1962c ? 01/02 note: 1. with i ol =1maandi oh =-1ma table 7 . 5v. power supply = +5v; t amb =25 c; f pclk = 1 mhz; duty cycle = 50%; c load 120 pf on digital outputs, analog outputs disconnected otherwise specified. parameter symbol test level min typ max unit power requirements positive supply voltage v cc 4.5 5 5.5 v digital positive supply current on v cc pin c load =0 i cc i iv 7 5 10 6 ma ma power dissipation on v cc c load =0 p cc i iv 35 25 50 30 mw mw current on v cc in nap mode i ccnap i10a analog output voltage range v avx i0 2.9v digital inputs logic compatibility cmos logic ? 0 ? voltage v il i0 1.2v logic ? 1 ? voltage v ih i3.6 vccv logic ? 0 ? current i il i-10 0a logic ? 1 ? current i ih i 0 10 a digital outputs logic compatibility cmos logic ? 0 ? voltage (1) v ol i1.5v logic ? 1 ? voltage (1) v oh i3.5 v
7 FCD4B14 1962c ? 01/02 . note: 1. with i ol =1maandi oh =-1ma table 8 . 3.3v. power supply = +3.3v; t amb =25 c; f pclk = 1 mhz; duty cycle = 50%; c load 120 pf on digital outputs, analog outputs disconnected otherwise specified parameter symbol test level min typ max unit power requirements positive supply voltage v cc 3.0 3.3 3.6 v digital positive supply current on v cc pin c load =0 i cc i iv 6 5 10 6 ma ma power dissipation on v cc c load =0 p cc i iv 20 17 33 20 mw mw current on v cc in nap mode i ccnap i10a analog output voltage range v av x i0 2.9v digital inputs logic compatibility cmos logic ? 0 ? voltage v il i0 0.8v logic ? 1 ? voltage v ih i2.3 vccv logic ? 0 ? current i il i-10 0a logic ? 1 ? current i ih i0 10a digital outputs logic compatibility cmos logic ? 0 ? voltage (1) v ol i0.6v logic ? 1 ? voltage (1) v oh i2.4 v
8 FCD4B14 1962c ? 01/02 . table 9 . switching performances. t amb =25 c; f pclk = 1 mhz; duty cycle = 50%; c load 120 pf on digital and analog outputs otherwise specified parameter symbol test level min typ max unit clock frequency f pclk i0.512mhz clock pulse width (high) t hclk i 250 ns clock pulse width (low) t lclk i 250 ns clock setup time (high)/reset falling edge t setup i0ns no data change t nooe iv 100 ns table 1 0. 5.0v. all power supplies = +5 v parameter symbol test level min typ max unit output delay from pclk to ackn rising edge t plhackn i85ns output delay from pclk to ackn falling edge t phlackn i80ns output delay from pclk to data output dxi t pdata i70ns output delay from pclk to analog output avx t pav i d e o i 170 ns output delay from oe to data high-z t dataz iv 25 ns output delay from oe to data output t zdata iv 29 ns table 1 1. 3.3v. all power supplies = +3.3 v parameter symbol test level min typ max unit output delay from pclk to ackn rising edge t plhackn i 110 ns output delay from pclk to ackn falling edge t phlackn i95ns output delay from pclk to data output dxi t pdata i85ns output delay from pclk to analog output avx t pav i d e o i 190 ns output delay from oe to data high-z t dataz iv 34 ns output delay from oe to data output t zdata iv 47 ns
9 FCD4B14 1962c ? 01/02 figure 2. reset figure 3. read one byte/two pixels t hrst t setup reset rst clock pclk data # n-1 t phlackn clock pclk acknowledge ackn data #n+2 data # n+1 data # n data #n data output do0-3, de0 -3 video analog output avo, ave data #n+1 t hclk t lclk f pclk t plhack t pdata t pavideo
10 FCD4B14 1962c ? 01/02 figure 4. output enable figure 5. no data change note: oe must not change during tnooe after the pclk falls. this is to ensure that the output drivers of the data is not driving cur- rent, to reduce the noise level on the power supply. hi-z hi-z output enable oe data output do0 -3, de0 -3 data output t zdata t dataz pclk t nooe oe
11 FCD4B14 1962c ? 01/02 figure 6. FCD4B14 block diagram functional description the circuit is divided into two main sections: sensor and data conversion. one particular column among 280+1 is selected in the sensor array (1), then each pixel of the selected column sends its electrical information to amplifiers (2) (one per line), then two lines at a time are selected (odd and even) so that two particular pixels send their information to the input of two 4-bit analog-to-digital converters (3), so 2 pixels can be read for each clock pulse (4). figure 7. functional description sensor each pixel is a sensor in itself. the sensor detects a temperature differential between the beginning of acquisition and the reading of information: this is the integration time. the integration time begins with a reset of the pixel to a predefined initial state. note that the integration time reset has nothing to do with the reset of the digital section. then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature variation between the reset and the end of the integration time, and on the duration of the integration time, electrical charges are generated at the pixel level. 2240 8 latches chip temperature sensor line sel odd ev en 8 lines of 280 columns of pixels 4-bit adc adc 8 1 dummy colum n 4 4 am p chip temperature stabilizati on ackn de0-3 do0-3 output enable analog output oe ave avo tpe tpp 1 8 pclk rst clock reset column selection 4-bit 8 latches chip temperature sensor column selection line sel odd ev en 8 lines of 280 columns of pixels 4-bit adc adc 8 1 dummy colum n 4 4 am p de0-3 do0-3 1 2 3 4 4-bit
12 FCD4B14 1962c ? 01/02 analog-to-digital converter/ reconstructing an 8-bit fingerprint image an analog-to-digital converter (adc) is used to convert the analog signal coming from the pixel into digital data that can be used by a processor. as the data rate for parallel port and usb is in the range of 1 mb per second and at least a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping speed for the finger, two 4-bit adcs have been used to output 2 pixels at a time on 1 byte. start sequence a reset is not necessary between each frame acquisition! start sequence must consist of: 1. set the rst pin to high 2. set the rst pin to low 3. send 4 clock pulses (due to pipe-line) 4. send clock pulses to skip the first frame note that the first frame never contains relevant information because the integration time is not correct. figure 8. start sequence reading the frames a frame consists of 280 true columns + 1 dummy column of 8 pixels. as two pixels are output at a time, a system must send 281x4 = 1124 clock pulses to read one frame. reset must be low when reading the frames. read one byte/output enable clock is taken into account on the falling edge and data are output on the rising edge. for each clock pulse, after the start sequence, a new byte is output on the do0-3, de0- 3 pins. this byte contains 2 pixels: 4-bit on do0-3 (odd pixels), 4-bit on de0-3 (even pixels). to output the data, the output enable (oe) pin must be low. when oe is high, the do0- 3 and de0-3 pins are in high impedance state. this enables an easy connection to a microprocessor bus without additional circuitry-it will enable data output by using a chip select signal. note that the FCD4B14 is always sending data: there is no data exchange to perform using read/write mode. power supply noise important: when a falling edge is applied on oe (i.e when the output enable becomes active), then some current is drained from the power supply to drive the 8 out- puts, producing some noise. it is important to avoid such noise just after the falling edge of the clock pclk, when the pixels information is evaluated: the timing diagram figure 5 and time t nooe defines the interval time where the power supply must be as quiet as possible. video output an analog signal is also available on pins ave and avo. note that video output is avail- able one clock pulse before the corresponding digital output (one clock pipe-line delay for the analog to digital conversion). 1 4 3 1 2 1 1124 clock pclk reset rs t 4+1124 clock pulses to skip the first fram e
13 FCD4B14 1962c ? 01/02 pixel order after a reset, pixel number one is located on the upper left corner, looking at the chip with bond pads to the right. for each column of 8 pixels, pixels 1-3-5-7 are output on odd data do0-3 pins, pixels 2-4-6-8 are output on even data de0-3 pins. most significant bit is bit #3, least significant is bit #0. figure 9. pixel order synchronization: the dummy column a dummy column has been added to the sensor to act as a specific pattern to detect the first pixel. so, 280 true columns + 1 dummy column are read for each frame. the 4 bytes of the dummy column contain a fixed pattern on the two first bytes, and tem- perature information on the last two bytes. note: x represents 0 or 1 the sequence 111x0000 111x0000 appears on every frame (exactly every 1124 clock pulses), so it is an easy pattern to recognize for synchronization purposes. b ond p ads pixel #1 (1,1) pixel #2233 (280,1) pixel #8 (1,8) pixel #2240 (280,8) dummy byte odd even dummy byte 1 db1: 111x 0000 dummy byte 2 db2: 111x 0000 dummy byte 3 db3: rrrr nnnn dummy byte 4 db4: tttt pppp
14 FCD4B14 1962c ? 01/02 thermometer the dummy bytes db3 and db4 contains some internal and temperature information. the even nibble nnnn in db3 can be used to measure an increase (or decrease) of the chip temperature, using the difference between two measures of the same physical device. the following table gives values in kelvin. for code 0 and 15, the absolute value is a minimum (saturation). when the image contrast becomes low because of a low temperature difference between the finger and the sensor, it is recommended to use the temperature stabiliza- tion circuitry to increase the temperature of two codes (i.e. from 8 to 10), to get at least an increase >1.4 kelvin of the sensor. this enables to recover enough contrast to get a proper fingeprint for recognition purpose. nnnn decimal nnnn binary temperature differential with code 8 in kelvin 15 1111 11.2 14 1110 8.4 13 1101 7 12 1100 5.6 11 1011 4.2 10 1010 2.8 91001 1.4 81000 0 70111 -1.4 60110 -2.8 50101 -4.2 40100 -5.6 30011 -7 20010 -8.4 10001 -11.2 00000 <-16.8
15 FCD4B14 1962c ? 01/02 integration time and clock jitter the FCD4B14 is not very sensitive to clock jitter (clock variation). the most important requirement is a regular integration time that ensures the frame reading rate is also as regular as possible, in order to get consistent fingerprint slices. if the integration time is not regular, contrast will vary from one frame to another. note that it is possible to introduce some waiting time between each set of 1124 clock pulses, but the overall time of one frame read must be regular. this waiting time is gen- erally the time needed by the processor to perform some calculation over the frame (to detect the finger, for instance). figure 10. read one frame figure 11. regular integration time clock pclk reset rst is lo w 123456 1124 1123 1122 1121 1120 1119 column 1 column 2 column 280 dummy column 281 pixels 1 & 2 3 & 4 5 & 6 7 & 8 1 & 2 3 & 4 7 & 8 db1 db2 db3 db 4 clock pclk regular integration time fram e n 1124 pulses fram e n+1 1124 pulses fram e n+2 1124 pulses fram e n+3 1124 pulse s
16 FCD4B14 1962c ? 01/02 power management nap mode several strategies are possible to reduce power consumption when not in use. the simplest and most efficient is to cut the power supply, using external means. a nap mode is also implemented in the FCD4B14. to activate this nap mode, user must: 1. set the reset rst pin to high. doing this, all analog sections of the device are internally powered down. 2. set the clock pclk pin to high (or low), thus stopping the entire digital section. 3. set the tpe pin to low or disconnect tpp to stop the temperature stabilization feature. 4. set output enable oe pin to high, so that output are forced in hiz. figure 12. nap mode in nap mode, all internal transistors are in shut mode. only leakage current is drained in power supply, generally less than the tested value. static current consumption when the clock is stopped (set to 1) and the reset is low (set to 0), the analog sections of the device drain some current and the digital section does not consume current if the outputs are connected to a standard cmos input (= no current is drained in the i/o). in this case the typical current value is 5 ma. this current does not depend on the voltage (i.e. it is almost the same from 3v to 5.5v). dynamic current consumption when the clock is running, the digital sections are consuming current, and particularly the outputs if they are heavily loaded. in any case, it should be less than the testing machine (120 pf load on each i/o), 50 pf maximum is recommended. connected to a usb interface chip (see application note 26 related to the fcdemo4 kit) at 5v, and running at about 1 mhz, the FCD4B14 consumes less than 7 ma on vcc pin. temperature stabilization power consumption (tpp pin) when the tpe pin is set to 1, current is drained via the tpp pin. the current is limited by the internal equivalent resistance given in table 4 and a possible external resistor. most of the time, tpe is set to 0 and no current is drained in tpp. when the image con- trast becomes low because of a low temperature differential (less than one kelvin), then it is recommended to set tpe to 1 during a short time so that the dissipated power in the chip elevates the temperature, enabling to recover contrast. the necessary time to increase the chip temperature of one kelvin depends on the dissipated power, the ther- mal capacity of the silicon sensor and the thermal resistance between the sensor and the surroundings. as a rule of thumb, dissipating 300 mw in the chip elevates the temperature of 1 kelvin in one second. with the 30 ? typical value, 300 mw is 3v applied on tpp. nap clock pclk reset rs t nap mode
17 FCD4B14 1962c ? 01/02 packaging: mechanical data figure 13. cob: top view (all dimensions in mm) figure 14. cob: bottom view (all dimensions in mm) at 0.4 height from b ref. at 0.4 height from b ref. *: including burrs 26.6 0.25* 0.2 min 5.20 max 1.5 max 0.83 0.50 dam and fill 9.45 0.5* 2.95 0.50 5.90 max 0.2 max 0.790 max 0.35 0.89 0.3 2.32 0.5 5.45 0.30 17.51 +0.07 -0.01 1.66 + 0.07 - 0.01 14 0.2 a b a 1.15 0.15 2.15 0.15 6.30 0.1 0.75 +0.33 -0.25 1 0.075 0.5 0.075 3.5 0.075 r0.75 +0.08 -0.12 (x3) 2 0.15 2 0.075 1.5 0.075 1 0.15 1.5 +0.15 -0.23 (x3) 23.85 0.1
18 FCD4B14 1962c ? 01/02 figure 15. dil package (all dimensions in mm) 0.08 0.75 max 3.15 0.32 0.81 0.05 0.46 0.05 0.25 max 1.1 0.1 2.54 0.13 22.86 0.13 4.75 0.1 60 0.08 25.4 0.25 9.36 0.15 6.34 0.15 0.1 min (2.45) (0.90) no.1 no.10 no.20 no.11 (0.20) 5.4 max 7.5 0.25 7.87 0.25 0.25 0.05 (7.62) 6.5 max
19 FCD4B14 1962c ? 01/02 ordering information package device fc d4b14 c ? atmel prefix package c: dip ceramic 20 pins cb: chip on board (cob) quality level ? : st andard temperature range com: 0 to +70 c c fingerchip family device type
? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty whichisdetailedinatmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 microcontrollers atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 atmel smart card ics scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive atmel heilbronn theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com at m e l ? is the registered trademarks of atmel. other terms and product names may be the trademarks of others. 1962c ? 01/02/xm

▲Up To Search▲

Price & Availability of FCD4B14

	To Download FCD4B14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .